Click here to return to the VHDL Reference Guide. (last edit: 24. september 2012)

Alias

Lets you give an alternative name for almost anything. Particularly useful for renaming a slice of an array, as it avoids the need to define a new signal or variable. Also allows one package to inherit procedures and functions from another package by aliasing them.

Syntax

  alias AliasName [: Datatype] is Name [Signature];

  Signature = [TypeName, ...] return TypeName
          

Placement

  PACKAGE Pack IS
    ... 
  END PACKAGE Pack;
  PACKAGE BODY Pack IS
    ... 
  END PACKAGE BODY Pack;
  Blk:BLOCK 
    ... 
  BEGIN 
    ... 
  END BLOCK Blk;
  ENTITY Ent IS
    ... 
  BEGIN 
    ... 
  END ENTITY Ent;
  ARCHITECTURE Arc OF Ent IS
    ... 
  BEGIN 
    ... 
  END ARCHITECTURE Arc;
  CONFIGURATION Conf OF Ent IS
    ... 
  END CONFIGURATION Conf;
  Proc:PROCESS(...) 
    ... 
  BEGIN 
    ... 
  END PROCESS Proc;
  PROCEDURE P(...) IS
    ... 
  BEGIN 
    ... 
  END PROCEDURE P;
  FUNCTION F(...) RETURN Tp IS
    ... 
  BEGIN
    ... 
  END FUNCTION F;

Rules

The AliasName may be an identifier, character or operator. An aliased procedure, function or enumeration literal must be identified unambiguously by a signature, which identifies the parameter types and return type (to allow for overloading).

Things to remember

The DataType and the Name being aliased must both be static, so an aliased slice name must have a static index constraint.

Synthesis

Not supported by many synthesis tools.

Example

  function F (A, B: Std_logic_vector) return BOOLEAN is
    alias P1: Std_logic_vector(1 to A'LENGTH) is A;
    alias P2: Std_logic_vector(1 to B'LENGTH) is B;
    -- Alias is used to create 2 local vectors with the same range
  begin
    for I in P1'RANGE loop
      if P1(I) = P2(I) then
        ...

  alias ">" is
    F[Std_logic_vector, Std_logic_vector] return BOOLEAN;
          

See Also

Constant